1. Field of the Invention
The present invention relates to a step-down power supply that lowers the voltage of externally supplied power to provide a load with power at a voltage equal to a reference voltage.
2. Description of the Related Art
FIG. 13 shows a simple step-down power supply 400 that can be integrated into, for example, a semiconductor memory chip. The output of a differential amplifier or comparator 401 is coupled through a control node G0 to the gate of a p-channel metal-oxide-semiconductor (PMOS) transistor 402. Power supplied from an external source at a voltage VCC is fed through the PMOS transistor 402 to drive internal load circuits 405 such as the sense amplifiers that amplify voltages from memory cells. The differential amplifier 401 compares the internal power supply voltage VDD with a reference voltage (Vref) and adjusts the conductivity (current-driving capability) of the PMOS transistor 402 so as to hold VDD at the reference voltage level.
If the current drawn by the loads 405 increases, as it does when the sense amplifiers are activated, for example, the internal power supply voltage VDD falls, but the differential amplifier 401 detects the fall and increases the conductivity of the PMOS transistor 402, thereby restoring VDD to the reference level. This feedback control takes place, however, with a certain delay. If the current draw increases abruptly, as illustrated in FIG. 14, VDD falls too rapidly for the differential amplifier 401 to keep up, and an unavoidable voltage droop occurs. The size of the droop can be reduced by enlarging the differential amplifier 401 and PMOS transistor 402 to increase their current-driving capability, but the attendant increase in chip size and current consumption by the step-down power supply 400 is undesirable.
Japanese Patent Application Publication No. H11-214617 suggests the modification shown in FIG. 15, in which a pull-down circuit 403 is added to pull the control node G0 down to the ground level (VSS) when the sense amplifiers in a memory circuit are turned on. The pull-down circuit 403 receives a sense amplifier activation signal (SA_ON). When SA_ON goes high, an internal pull-down signal in the pull-down circuit 403 goes high for a predetermined interval, turning on a transistor (not shown) that connects node G0 to ground (VSS). The conductivity of the PMOS transistor 402 then increases rapidly and the VDD voltage droop is much reduced, as illustrated in FIG. 16.
FIG. 17 shows another conventional step-down power supply. This step-down power supply 1 receives power from an external source at a voltage VCC, such as 3.3 V, for example, lowers the external power supply voltage to generate an internal power supply voltage VDD equal to a reference voltage Vref, such as 2.5 V, for example, and provides the internal power supply voltage to a load circuit 2. The step-down power supply 1 comprises a reference voltage generator 10, a control circuit 30, and a stepped-down voltage output circuit 40. The reference voltage generator 10 generates the reference voltage Vref. The control circuit 30 switches a step-down control signal S30 between a high level and a low level according to the amount of current drawn by the load circuit 2. The stepped-down voltage output circuit 40 receives the reference voltage Vref and the step-down control signal S30 and outputs the internal power supply voltage VDD.
The stepped-down voltage output circuit 40 comprises PMOS transistors 41, 42, 47, n-channel metal-oxide-semiconductor (NMOS) transistors 43, 44, 45, and a constant-current source 46. PMOS transistor 41 has its source connected to the VCC power source, its drain connected to a node N42, and its gate connected to a node N41. PMOS transistor 42 has its source connected to the VCC power source and its drain and gate connected to node N41. NMOS transistor 43 has its source connected to a node N43, its drain connected to node N42, and its gate connected to a node N45. NMOS transistor 44 has its source connected to node N43, its drain connected to node N41, and its gate connected to a node N44. NMOS transistor 45 has its source connected to ground (VSS), its drain connected to node N43, and its gate connected to a node N46. PMOS transistor 47 has its source connected to the VCC power source, its drain connected to node N44, and its gate connected to node N42. The constant-current source 46 is connected between node N43 and ground. Node N45 receives the reference voltage Vref. Node N46 receives the step-down control signal S30. Node N44 outputs the internal power supply voltage VDD.
PMOS transistors 41 and 42 form a current mirror structure with identical source potentials and identical gate-source voltages. In the steady state, the source-drain currents I41 and I42 of PMOS transistors 41 and 42 are identical, and the potentials at nodes N41 and N42 are both equal to VCC−Vtp, where Vtp is the source-drain voltage of PMOS transistors 41 and 42. The source-drain currents I43 and I44 of NMOS transistors 43 and 44 are also identical (I41=I42=I43=I44), which implies that the gate potentials of NMOS transistors 43 and 44 are equal; the internal power supply voltage VDD is therefore equal to the reference voltage Vref. If the current IVDD drawn by the load circuit 2 varies, feedback in the stepped-down voltage output circuit 40 operates to maintain the equality of VDD and Vref by adjusting the potential at node N42, thereby adjusting the conductivity of PMOS transistor 47.
The response speed of this feedback control loop depends on the rate at which the gate capacitances of the transistors, especially PMOS transistor 47, can be charged and discharged. This depends on the magnitude of currents I41, I42, I43, and I44; that is, the response speed of the stepped-down voltage output circuit 40 depends on its current consumption. While the load circuit 2 is in the standby state and draws a small and relatively constant amount of current IVDD, rapid feedback control is not necessary, so the step-down control signal S30 is driven low, turning off NMOS transistor 45 and reducing the current consumption of the stepped-down voltage output circuit 40. When the load circuit 2 is active and draws a larger and more variable amount of current IVDD, the step-down control signal S30 is driven high, turning on NMOS transistor 45 to increase the current flow through the stepped-down voltage output circuit 40 and provide a faster feedback response.
The current IVDD drawn by the load circuit 2 is the source-drain current I47 of PMOS transistor 47 (I47=IVDD). When the load circuit 2 is in the standby state and NMOS transistor 45 is turned off, the steady-state potential at node N42 is VCC−Vtp1 , where Vtp1 is comparatively small. The relatively slow response in this state is illustrated in FIG. 18: if the reference voltage Vref rises from its normal level V40 to a higher level V41 while the step-down control signal S30 is low, the internal power supply voltage VDD rises comparatively slowly from V40 to the new level V41. During this rise, the potential at node N42 temporarily drops.
When the load circuit 2 is in the active state, the step-down control signal S30 is high, NMOS transistor 45 is turned on, the sum (I43+I44) of currents I43 and I44 increases from I46 to I45+I46, and the sum (I41+I42) of currents I41 and I42 also increases from I46 to I45+I46. The potential at node N42 in this state is now VCC−Vtp2, where Vtp2 is comparatively large. If the reference voltage Vref rises from its normal level V40 to a higher level V41 in this state, the internal power supply voltage VDD rises comparatively quickly from V40 to the new level V41, as shown at the bottom of FIG. 18, but the potential at node N42 still drops temporarily, and the drop is greater than the corresponding drop in the standby-state when S30 is low.
FIG. 18 shows that the stepped-down voltage output circuit 40 responds faster to a change in the reference voltage Vref when the step-down control signal S30 is high than when S30 is low. Similarly, the response to a change in the current IVDD drawn by the load circuit 2 is faster when the S30 is high than when S30 is low.
The voltage changes in FIG. 18 can be explained as follows. In the state in which the step-down control signal S30 is low, for example, when the reference voltage Vref rises from V40 to a higher voltage V41, the gate-source voltage of NMOS transistor 43 becomes higher than the gate-source voltage of NMOS transistor 44, and the drain-source current I43 of NMOS transistor 43 becomes greater than the drain-source current I44 of NMOS transistor 44 (I43>I44). Accordingly, the voltage at node N42 falls below VCC−Vtp1 . This increases the gate-source voltage and therefore the conductivity of PMOS transistor 47, thereby increasing the internal power supply voltage VDD.
A problem with the conventional step-down power supply in FIG. 15 is that if the response of the feedback control system including the differential amplifier is slow, after being pulled down, the control node G0 cannot return quickly to its normal potential level, and may remain at a comparatively low level even after the current drawn by the internal load circuits 405 has fallen back to the original level. As a result, the conductivity of PMOS transistor 402 is too high, and the internal power supply voltage VDD increases, as shown in FIG. 19. This problem is observed when the rapid rise in current draw that occurs when the internal load circuit is activated is immediately followed by a decline in the current draw.
The conventional step-down power supply in FIG. 17 is apt to malfunction when the level of the step-down control signal changes. The cause of the malfunction will be described with reference to FIG. 20, which shows voltage, current, and timing waveforms illustrating the operation of the stepped-down voltage output circuit 40.
The load circuit 2 draws current IVDD equal to I1 in the standby state and I2 in the active state. When the load circuit 2 enters the active state, IVDD abruptly increases from I1 to I2, causing the step-down control signal S30 to go high. The current flowing between node N43 and ground (VSS) abruptly increases from I46 to I46+I45 and the voltage at node N43 abruptly decreases from a value Vtn to a lower value Vtn−α, where α depends on the characteristics of the PMOS and NMOS transistors used. The voltage drop at node N43 is coupled through the gate-source capacitance of NMOS transistor 43 to node N45, causing the reference voltage Vref to decrease temporarily from V40 to a lower value V40−ΔV1. The voltage at node N42 likewise decreases temporarily to a value lower than both VCC−Vtp3 (the normal value in the standby state) and VCC−Vtp4 (the normal value in the active state). The internal power supply voltage VDD also drops temporarily, mimicking the change in the reference voltage Vref. After a certain delay, the reference voltage generator 10 restores the reference voltage Vref to V40 and the internal supply voltage VDD also returns to V40.
When the load circuit 2 returns to the standby state and its current draw IVDD decreases from I2 to I1, the step-down control signal S30 goes low, the current flowing between node N43 and ground to decreases from I46+I45 to I46, and the voltage at node N43 increases from Vtn−α to Vtn. The voltage rise at node N43 is coupled through the gate-source capacitance of NMOS transistor 43 to node N45, causing the reference voltage Vref to rise temporarily to V40+ΔV2. The internal power supply voltage VDD likewise rises to V40+ΔV2, while node N42 rises to a level higher than both VCC−Vtp3 and VCC−Vtp4 . After a delay, the reference voltage generator 10 restores the reference voltage Vref to V40, node N42 returns to VCC−Vtp3 , and the internal power supply voltage VDD returns to V40.
The temporary rise and fall of the internal power supply voltage VDD to levels above and below V40, caused by the temporary excursions of the potential at node N42 to levels above VCC−Vtp3 and below VCC−Vtp4 , temporarily degrades the internal response speed, timing margin, and input voltage margin of the load circuit 2, and can cause the load circuit to malfunction.